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Text File  |  2000-03-13  |  42KB  |  1,133 lines
  1. #ifndef __INLINE_MACROS_H
  2. #define __INLINE_MACROS_H
  3.  
  4. /*
  5.    General macros for Amiga function calls. Not all the possibilities have
  6.    been created - only the ones which exist in OS 3.1. Third party libraries
  7.    and future versions of AmigaOS will maybe need some new ones...
  8.  
  9.    LPX - functions that take X arguments.
  10.  
  11.    Modifiers (variations are possible):
  12.    NR - no return (void),
  13.    A4, A5 - "a4" or "a5" is used as one of the arguments,
  14.    UB - base will be given explicitly by user (see cia.resource).
  15.    FP - one of the parameters has type "pointer to function".
  16.  
  17.    "bt" arguments are not used - they are provided for backward compatibility
  18.    only.
  19.    Actually..the "bt" parameter is needed because otherwise the macro doesn`t
  20.    work for some reason i don`t know gcc puts an empty argument at the position
  21.    before the argument bn and without the placeholder "bt".
  22.    I think it has something to do with #define *_BASE_NAME
  23.  
  24.    the (cm1==IF_CACHEFLUSHAREA) conditional is optimized away
  25. */
  26.  
  27. #ifndef __INLINE_STUB_H
  28. #include <powerup/ppcinline/stubs.h>
  29. #endif
  30.  
  31. #ifndef POWERUP_PPCLIB_INTERFACE_H
  32. #include <powerup/ppclib/interface.h>
  33. #endif
  34.  
  35. #define LP0(offs, rt, name, bt, bn, cm1, cs1, cl1, cm2, cs2, cl2 )    \
  36. ({                                \
  37.    struct Caos    MyCaos;                        \
  38.    register struct Caos *MyCaosReg __asm("r3") = &MyCaos;    \
  39.    {                                \
  40.       register rt _##name##_re __asm("r3");            \
  41.       MyCaos.a6            =(ULONG) bn;            \
  42.       MyCaos.M68kCacheMode    =    cm1;            \
  43.       if ((cm1==IF_CACHEFLUSHAREA) || (cm1==IF_CACHEINVALIDAREA))    \
  44.       {                                \
  45.         MyCaos.M68kStart    =    cs1;            \
  46.         MyCaos.M68kLength    =    cl1;            \
  47.       }                                \
  48.       MyCaos.PPCCacheMode    =    cm2;            \
  49.       if ((cm2==IF_CACHEFLUSHAREA) || (cm2==IF_CACHEINVALIDAREA))    \
  50.       {                                \
  51.         MyCaos.PPCStart        =    cs2;            \
  52.         MyCaos.PPCLength    =    cl2;            \
  53.       }                                \
  54.       MyCaos.caos_Un.Offset    =    (-offs);        \
  55.       __asm volatile ("bl PPCCallOS"                \
  56.       : "=r" (_##name##_re)                    \
  57.       : "r" (MyCaosReg)                      \
  58.       : "r0", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12",  "lr", "ctr", "cc", "memory");    \
  59.       _##name##_re;                        \
  60.    }                                \
  61. })
  62.  
  63. #define LP0NR(offs, name, bt, bn, cm1, cs1, cl1, cm2, cs2, cl2 )    \
  64. ({                                \
  65.    struct Caos    MyCaos;                        \
  66.    register struct Caos *MyCaosReg __asm("r3") = &MyCaos;    \
  67.    {                                \
  68.       MyCaos.a6            =(ULONG) bn;            \
  69.       MyCaos.M68kCacheMode    =    cm1;            \
  70.       if ((cm1==IF_CACHEFLUSHAREA) || (cm1==IF_CACHEINVALIDAREA))    \
  71.       {                                \
  72.         MyCaos.M68kStart    =    cs1;            \
  73.         MyCaos.M68kLength    =    cl1;            \
  74.       }                                \
  75.       MyCaos.PPCCacheMode    =    cm2;            \
  76.       if ((cm2==IF_CACHEFLUSHAREA) || (cm2==IF_CACHEINVALIDAREA))    \
  77.       {                                \
  78.         MyCaos.PPCStart        =    cs2;            \
  79.         MyCaos.PPCLength    =    cl2;            \
  80.       }                                \
  81.       MyCaos.caos_Un.Offset    =    (-offs);        \
  82.       __asm volatile ("bl PPCCallOS"                \
  83.       :                                \
  84.       : "r" (MyCaosReg)                      \
  85.       : "r0", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12",  "lr", "ctr", "cc", "memory");    \
  86.    }                                \
  87. })
  88.  
  89. #define LP1(offs, rt, name, t1, v1, r1, bt, bn, cm1, cs1, cl1, cm2, cs2, cl2 )    \
  90. ({                                \
  91.    struct Caos    MyCaos;                        \
  92.    register struct Caos *MyCaosReg __asm("r3") = &MyCaos;    \
  93.    {                                \
  94.       register rt _##name##_re __asm("r3");            \
  95.       MyCaos.##r1        =(ULONG) v1;            \
  96.       MyCaos.a6            =(ULONG) bn;            \
  97.       MyCaos.M68kCacheMode    =    cm1;            \
  98.       if ((cm1==IF_CACHEFLUSHAREA) || (cm1==IF_CACHEINVALIDAREA))    \
  99.       {                                \
  100.         MyCaos.M68kStart    =    cs1;            \
  101.         MyCaos.M68kLength    =    cl1;            \
  102.       }                                \
  103.       MyCaos.PPCCacheMode    =    cm2;            \
  104.       if ((cm2==IF_CACHEFLUSHAREA) || (cm2==IF_CACHEINVALIDAREA))    \
  105.       {                                \
  106.         MyCaos.PPCStart        =    cs2;            \
  107.         MyCaos.PPCLength    =    cl2;            \
  108.       }                                \
  109.       MyCaos.caos_Un.Offset    =    (-offs);        \
  110.       __asm volatile ("bl PPCCallOS"                \
  111.       : "=r" (_##name##_re)                    \
  112.       : "r" (MyCaosReg)                      \
  113.       : "r0", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12",  "lr", "ctr", "cc", "memory");    \
  114.       _##name##_re;                        \
  115.    }                                \
  116. })
  117.  
  118. #define LP1NR(offs, name, t1, v1, r1, bt, bn, cm1, cs1, cl1, cm2, cs2, cl2 )    \
  119. ({                                \
  120.    struct Caos    MyCaos;                        \
  121.    register struct Caos *MyCaosReg __asm("r3") = &MyCaos;    \
  122.    {                                \
  123.       MyCaos.##r1        =(ULONG) v1;            \
  124.       MyCaos.a6            =(ULONG) bn;            \
  125.       MyCaos.M68kCacheMode    =    cm1;            \
  126.       if ((cm1==IF_CACHEFLUSHAREA) || (cm1==IF_CACHEINVALIDAREA))    \
  127.       {                                \
  128.         MyCaos.M68kStart    =    cs1;            \
  129.         MyCaos.M68kLength    =    cl1;            \
  130.       }                                \
  131.       MyCaos.PPCCacheMode    =    cm2;            \
  132.       if ((cm2==IF_CACHEFLUSHAREA) || (cm2==IF_CACHEINVALIDAREA))    \
  133.       {                                \
  134.         MyCaos.PPCStart        =    cs2;            \
  135.         MyCaos.PPCLength    =    cl2;            \
  136.       }                                \
  137.       MyCaos.caos_Un.Offset    =    (-offs);        \
  138.       __asm volatile ("bl PPCCallOS"                \
  139.       :                                \
  140.       : "r" (MyCaosReg)                      \
  141.       : "r0", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12",  "lr", "ctr", "cc", "memory");    \
  142.    }                                \
  143. })
  144.  
  145. /* Only graphics.library/AttemptLockLayerRom() */
  146. #define LP1A5(offs, rt, name, t1, v1, r1, bt, bn, cm1, cs1, cl1, cm2, cs2, cl2 )    \
  147. ({                                \
  148.    struct Caos    MyCaos;                        \
  149.    register struct Caos *MyCaosReg __asm("r3") = &MyCaos;    \
  150.    {                                \
  151.       register rt _##name##_re __asm("r3");            \
  152.       MyCaos.##r1        =(ULONG) v1;            \
  153.       MyCaos.a6            =(ULONG) bn;            \
  154.       MyCaos.M68kCacheMode    =    cm1;            \
  155.       if ((cm1==IF_CACHEFLUSHAREA) || (cm1==IF_CACHEINVALIDAREA))    \
  156.       {                                \
  157.         MyCaos.M68kStart    =    cs1;            \
  158.         MyCaos.M68kLength    =    cl1;            \
  159.       }                                \
  160.       MyCaos.PPCCacheMode    =    cm2;            \
  161.       if ((cm2==IF_CACHEFLUSHAREA) || (cm2==IF_CACHEINVALIDAREA))    \
  162.       {                                \
  163.         MyCaos.PPCStart        =    cs2;            \
  164.         MyCaos.PPCLength    =    cl2;            \
  165.       }                                \
  166.       MyCaos.caos_Un.Offset    =    (-offs);        \
  167.       __asm volatile ("bl PPCCallOS"                \
  168.       : "=r" (_##name##_re)                    \
  169.       : "r" (MyCaosReg)                      \
  170.       : "r0", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12",  "lr", "ctr", "cc", "memory");    \
  171.       _##name##_re;                        \
  172.    }                                \
  173. })
  174.  
  175. /* Only graphics.library/LockLayerRom() and graphics.library/UnlockLayerRom() */
  176. #define LP1NRA5(offs, name, t1, v1, r1, bt, bn, cm1, cs1, cl1, cm2, cs2, cl2 )    \
  177. ({                                \
  178.    struct Caos    MyCaos;                        \
  179.    register struct Caos *MyCaosReg __asm("r3") = &MyCaos;    \
  180.    {                                \
  181.       MyCaos.##r1        =(ULONG) v1;            \
  182.       MyCaos.a6            =(ULONG) bn;            \
  183.       MyCaos.M68kCacheMode    =    cm1;            \
  184.       if ((cm1==IF_CACHEFLUSHAREA) || (cm1==IF_CACHEINVALIDAREA))    \
  185.       {                                \
  186.         MyCaos.M68kStart    =    cs1;            \
  187.         MyCaos.M68kLength    =    cl1;            \
  188.       }                                \
  189.       MyCaos.PPCCacheMode    =    cm2;            \
  190.       if ((cm2==IF_CACHEFLUSHAREA) || (cm2==IF_CACHEINVALIDAREA))    \
  191.       {                                \
  192.         MyCaos.PPCStart        =    cs2;            \
  193.         MyCaos.PPCLength    =    cl2;            \
  194.       }                                \
  195.       MyCaos.caos_Un.Offset    =    (-offs);        \
  196.       __asm volatile ("bl PPCCallOS"                \
  197.       :                                \
  198.       : "r" (MyCaosReg)                      \
  199.       : "r0", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12",  "lr", "ctr", "cc", "memory");    \
  200.    }                                \
  201. })
  202.  
  203. /* Only exec.library/Supervisor() */
  204. #define LP1A5FP(offs, rt, name, t1, v1, r1, bt, bn, fpt, cm1, cs1, cl1, cm2, cs2, cl2 )    \
  205. ({                                \
  206.    typedef fpt;                            \
  207.    struct Caos    MyCaos;                        \
  208.    register struct Caos *MyCaosReg __asm("r3") = &MyCaos;    \
  209.    {                                \
  210.       register rt _##name##_re __asm("r3");            \
  211.       MyCaos.##r1        =(ULONG) v1;            \
  212.       MyCaos.a6            =(ULONG) bn;            \
  213.       MyCaos.M68kCacheMode    =    cm1;            \
  214.       if ((cm1==IF_CACHEFLUSHAREA) || (cm1==IF_CACHEINVALIDAREA))    \
  215.       {                                \
  216.         MyCaos.M68kStart    =    cs1;            \
  217.         MyCaos.M68kLength    =    cl1;            \
  218.       }                                \
  219.       MyCaos.PPCCacheMode    =    cm2;            \
  220.       if ((cm2==IF_CACHEFLUSHAREA) || (cm2==IF_CACHEINVALIDAREA))    \
  221.       {                                \
  222.         MyCaos.PPCStart        =    cs2;            \
  223.         MyCaos.PPCLength    =    cl2;            \
  224.       }                                \
  225.       MyCaos.caos_Un.Offset    =    (-offs);        \
  226.       __asm volatile ("bl PPCCallOS"                \
  227.       : "=r" (_##name##_re)                    \
  228.       : "r" (MyCaosReg)                      \
  229.       : "r0", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12",  "lr", "ctr", "cc", "memory");    \
  230.       _##name##_re;                        \
  231.    }                                \
  232. })
  233.  
  234.  
  235. #define LP2(offs, rt, name, t1, v1, r1, t2, v2, r2, bt, bn, cm1, cs1, cl1, cm2, cs2, cl2 )    \
  236. ({                                \
  237.    struct Caos    MyCaos;                        \
  238.    register struct Caos *MyCaosReg __asm("r3") = &MyCaos;    \
  239.    {                                \
  240.       register rt _##name##_re __asm("r3");            \
  241.       MyCaos.##r1        =(ULONG) v1;            \
  242.       MyCaos.##r2        =(ULONG) v2;            \
  243.       MyCaos.a6            =(ULONG) bn;            \
  244.       MyCaos.M68kCacheMode    =    cm1;            \
  245.       if ((cm1==IF_CACHEFLUSHAREA) || (cm1==IF_CACHEINVALIDAREA))    \
  246.       {                                \
  247.         MyCaos.M68kStart    =    cs1;            \
  248.         MyCaos.M68kLength    =    cl1;            \
  249.       }                                \
  250.       MyCaos.PPCCacheMode    =    cm2;            \
  251.       if ((cm2==IF_CACHEFLUSHAREA) || (cm2==IF_CACHEINVALIDAREA))    \
  252.       {                                \
  253.         MyCaos.PPCStart        =    cs2;            \
  254.         MyCaos.PPCLength    =    cl2;            \
  255.       }                                \
  256.       MyCaos.caos_Un.Offset    =    (-offs);        \
  257.       __asm volatile ("bl PPCCallOS"                \
  258.       : "=r" (_##name##_re)                    \
  259.       : "r" (MyCaosReg)                      \
  260.       : "r0", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12",  "lr", "ctr", "cc", "memory");    \
  261.       _##name##_re;                        \
  262.    }                                \
  263. })
  264.  
  265. #define LP2NR(offs, name, t1, v1, r1, t2, v2, r2, bt, bn, cm1, cs1, cl1, cm2, cs2, cl2 )    \
  266. ({                                \
  267.    struct Caos    MyCaos;                        \
  268.    register struct Caos *MyCaosReg __asm("r3") = &MyCaos;    \
  269.    {                                \
  270.       MyCaos.##r1        =(ULONG) v1;            \
  271.       MyCaos.##r2        =(ULONG) v2;            \
  272.       MyCaos.a6            =(ULONG) bn;            \
  273.       MyCaos.M68kCacheMode    =    cm1;            \
  274.       if ((cm1==IF_CACHEFLUSHAREA) || (cm1==IF_CACHEINVALIDAREA))    \
  275.       {                                \
  276.         MyCaos.M68kStart    =    cs1;            \
  277.         MyCaos.M68kLength    =    cl1;            \
  278.       }                                \
  279.       MyCaos.PPCCacheMode    =    cm2;            \
  280.       if ((cm2==IF_CACHEFLUSHAREA) || (cm2==IF_CACHEINVALIDAREA))    \
  281.       {                                \
  282.         MyCaos.PPCStart        =    cs2;            \
  283.         MyCaos.PPCLength    =    cl2;            \
  284.       }                                \
  285.       MyCaos.caos_Un.Offset    =    (-offs);        \
  286.       __asm volatile ("bl PPCCallOS"                \
  287.       :                                \
  288.       : "r" (MyCaosReg)                      \
  289.       : "r0", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12",  "lr", "ctr", "cc", "memory");    \
  290.    }                                \
  291. })
  292.  
  293. /* Only cia.resource/AbleICR() and cia.resource/SetICR() */
  294. #define LP2UB(offs, rt, name, t1, v1, r1, t2, v2, r2, cm1, cs1, cl1, cm2, cs2, cl2 )    \
  295. ({                                \
  296.    struct Caos    MyCaos;                        \
  297.    register struct Caos *MyCaosReg __asm("r3") = &MyCaos;    \
  298.    {                                \
  299.       register rt _##name##_re __asm("r3");            \
  300.       MyCaos.##r1        =(ULONG) v1;            \
  301.       MyCaos.##r2        =(ULONG) v2;            \
  302.       MyCaos.M68kCacheMode    =    cm1;            \
  303.       if ((cm1==IF_CACHEFLUSHAREA) || (cm1==IF_CACHEINVALIDAREA))    \
  304.       {                                \
  305.         MyCaos.M68kStart    =    cs1;            \
  306.         MyCaos.M68kLength    =    cl1;            \
  307.       }                                \
  308.       MyCaos.PPCCacheMode    =    cm2;            \
  309.       if ((cm2==IF_CACHEFLUSHAREA) || (cm2==IF_CACHEINVALIDAREA))    \
  310.       {                                \
  311.         MyCaos.PPCStart        =    cs2;            \
  312.         MyCaos.PPCLength    =    cl2;            \
  313.       }                                \
  314.       MyCaos.caos_Un.Offset    =    (-offs);        \
  315.       __asm volatile ("bl PPCCallOS"                \
  316.       : "=r" (_##name##_re)                    \
  317.       : "r" (MyCaosReg)                      \
  318.       : "r0", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12",  "lr", "ctr", "cc", "memory");    \
  319.       _##name##_re;                        \
  320.    }                                \
  321. })
  322.  
  323. /* Only dos.library/InternalUnLoadSeg() */
  324. #define LP2FP(offs, rt, name, t1, v1, r1, t2, v2, r2, bt, bn, fpt, cm1, cs1, cl1, cm2, cs2, cl2 )    \
  325. ({                                \
  326.    typedef fpt;                            \
  327.    struct Caos    MyCaos;                        \
  328.    register struct Caos *MyCaosReg __asm("r3") = &MyCaos;    \
  329.    {                                \
  330.       register rt _##name##_re __asm("r3");            \
  331.       MyCaos.##r1        =(ULONG) v1;            \
  332.       MyCaos.##r2        =(ULONG) v2;            \
  333.       MyCaos.a6            =(ULONG) bn;            \
  334.       MyCaos.M68kCacheMode    =    cm1;            \
  335.       if ((cm1==IF_CACHEFLUSHAREA) || (cm1==IF_CACHEINVALIDAREA))    \
  336.       {                                \
  337.         MyCaos.M68kStart    =    cs1;            \
  338.         MyCaos.M68kLength    =    cl1;            \
  339.       }                                \
  340.       MyCaos.PPCCacheMode    =    cm2;            \
  341.       if ((cm2==IF_CACHEFLUSHAREA) || (cm2==IF_CACHEINVALIDAREA))    \
  342.       {                                \
  343.         MyCaos.PPCStart        =    cs2;            \
  344.         MyCaos.PPCLength    =    cl2;            \
  345.       }                                \
  346.       MyCaos.caos_Un.Offset    =    (-offs);        \
  347.       __asm volatile ("bl PPCCallOS"                \
  348.       : "=r" (_##name##_re)                    \
  349.       : "r" (MyCaosReg)                      \
  350.       : "r0", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12",  "lr", "ctr", "cc", "memory");    \
  351.       _##name##_re;                        \
  352.    }                                \
  353. })
  354.  
  355. #define LP3(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, bt, bn, cm1, cs1, cl1, cm2, cs2, cl2 )    \
  356. ({                                \
  357.    struct Caos    MyCaos;                        \
  358.    register struct Caos *MyCaosReg __asm("r3") = &MyCaos;    \
  359.    {                                \
  360.       register rt _##name##_re __asm("r3");            \
  361.       MyCaos.##r1        =(ULONG) v1;            \
  362.       MyCaos.##r2        =(ULONG) v2;            \
  363.       MyCaos.##r3        =(ULONG) v3;            \
  364.       MyCaos.a6            =(ULONG) bn;            \
  365.       MyCaos.M68kCacheMode    =    cm1;            \
  366.       if ((cm1==IF_CACHEFLUSHAREA) || (cm1==IF_CACHEINVALIDAREA))    \
  367.       {                                \
  368.         MyCaos.M68kStart    =    cs1;            \
  369.         MyCaos.M68kLength    =    cl1;            \
  370.       }                                \
  371.       MyCaos.PPCCacheMode    =    cm2;            \
  372.       if ((cm2==IF_CACHEFLUSHAREA) || (cm2==IF_CACHEINVALIDAREA))    \
  373.       {                                \
  374.         MyCaos.PPCStart        =    cs2;            \
  375.         MyCaos.PPCLength    =    cl2;            \
  376.       }                                \
  377.       MyCaos.caos_Un.Offset    =    (-offs);        \
  378.       __asm volatile ("bl PPCCallOS"                \
  379.       : "=r" (_##name##_re)                    \
  380.       : "r" (MyCaosReg)                      \
  381.       : "r0", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12",  "lr", "ctr", "cc", "memory");    \
  382.       _##name##_re;                        \
  383.    }                                \
  384. })
  385.  
  386. #define LP3NR(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, bt, bn, cm1, cs1, cl1, cm2, cs2, cl2 )    \
  387. ({                                \
  388.    struct Caos    MyCaos;                        \
  389.    register struct Caos *MyCaosReg __asm("r3") = &MyCaos;    \
  390.    {                                \
  391.       MyCaos.##r1        =(ULONG) v1;            \
  392.       MyCaos.##r2        =(ULONG) v2;            \
  393.       MyCaos.##r3        =(ULONG) v3;            \
  394.       MyCaos.a6            =(ULONG) bn;            \
  395.       MyCaos.M68kCacheMode    =    cm1;            \
  396.       if ((cm1==IF_CACHEFLUSHAREA) || (cm1==IF_CACHEINVALIDAREA))    \
  397.       {                                \
  398.         MyCaos.M68kStart    =    cs1;            \
  399.         MyCaos.M68kLength    =    cl1;            \
  400.       }                                \
  401.       MyCaos.PPCCacheMode    =    cm2;            \
  402.       if ((cm2==IF_CACHEFLUSHAREA) || (cm2==IF_CACHEINVALIDAREA))    \
  403.       {                                \
  404.         MyCaos.PPCStart        =    cs2;            \
  405.         MyCaos.PPCLength    =    cl2;            \
  406.       }                                \
  407.       MyCaos.caos_Un.Offset    =    (-offs);        \
  408.       __asm volatile ("bl PPCCallOS"                \
  409.       :                                \
  410.       : "r" (MyCaosReg)                      \
  411.       : "r0", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12",  "lr", "ctr", "cc", "memory");    \
  412.    }                                \
  413. })
  414.  
  415. /* Only cia.resource/AddICRVector() */
  416. #define LP3UB(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, cm1, cs1, cl1, cm2, cs2, cl2 )    \
  417. ({                                \
  418.    struct Caos    MyCaos;                        \
  419.    register struct Caos *MyCaosReg __asm("r3") = &MyCaos;    \
  420.    {                                \
  421.       register rt _##name##_re __asm("r3");            \
  422.       MyCaos.##r1        =(ULONG) v1;            \
  423.       MyCaos.##r2        =(ULONG) v2;            \
  424.       MyCaos.##r3        =(ULONG) v3;            \
  425.       MyCaos.M68kCacheMode    =    cm1;            \
  426.       if ((cm1==IF_CACHEFLUSHAREA) || (cm1==IF_CACHEINVALIDAREA))    \
  427.       {                                \
  428.         MyCaos.M68kStart    =    cs1;            \
  429.         MyCaos.M68kLength    =    cl1;            \
  430.       }                                \
  431.       MyCaos.PPCCacheMode    =    cm2;            \
  432.       if ((cm2==IF_CACHEFLUSHAREA) || (cm2==IF_CACHEINVALIDAREA))    \
  433.       {                                \
  434.         MyCaos.PPCStart        =    cs2;            \
  435.         MyCaos.PPCLength    =    cl2;            \
  436.       }                                \
  437.       MyCaos.caos_Un.Offset    =    (-offs);        \
  438.       __asm volatile ("bl PPCCallOS"                \
  439.       : "=r" (_##name##_re)                    \
  440.       : "r" (MyCaosReg)                      \
  441.       : "r0", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12",  "lr", "ctr", "cc", "memory");    \
  442.       _##name##_re;                        \
  443.    }                                \
  444. })
  445.  
  446. /* Only cia.resource/RemICRVector() */
  447. #define LP3NRUB(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, cm1, cs1, cl1, cm2, cs2, cl2 )    \
  448. ({                                \
  449.    struct Caos    MyCaos;                        \
  450.    register struct Caos *MyCaosReg __asm("r3") = &MyCaos;    \
  451.    {                                \
  452.       MyCaos.##r1        =(ULONG) v1;            \
  453.       MyCaos.##r2        =(ULONG) v2;            \
  454.       MyCaos.##r3        =(ULONG) v3;            \
  455.       MyCaos.M68kCacheMode    =    cm1;            \
  456.       if ((cm1==IF_CACHEFLUSHAREA) || (cm1==IF_CACHEINVALIDAREA))    \
  457.       {                                \
  458.         MyCaos.M68kStart    =    cs1;            \
  459.         MyCaos.M68kLength    =    cl1;            \
  460.       }                                \
  461.       MyCaos.PPCCacheMode    =    cm2;            \
  462.       if ((cm2==IF_CACHEFLUSHAREA) || (cm2==IF_CACHEINVALIDAREA))    \
  463.       {                                \
  464.         MyCaos.PPCStart        =    cs2;            \
  465.         MyCaos.PPCLength    =    cl2;            \
  466.       }                                \
  467.       MyCaos.caos_Un.Offset    =    (-offs);        \
  468.       __asm volatile ("bl PPCCallOS"                \
  469.       :                                \
  470.       : "r" (MyCaosReg)                      \
  471.       : "r0", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12",  "lr", "ctr", "cc", "memory");    \
  472.    }                                \
  473. })
  474.  
  475. /* Only exec.library/SetFunction() */
  476. #define LP3FP(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, bt, bn, fpt, cm1, cs1, cl1, cm2, cs2, cl2 )    \
  477. ({                                \
  478.    typedef fpt;                            \
  479.    struct Caos    MyCaos;                        \
  480.    register struct Caos *MyCaosReg __asm("r3") = &MyCaos;    \
  481.    {                                \
  482.       register rt _##name##_re __asm("r3");            \
  483.       MyCaos.##r1        =(ULONG) v1;            \
  484.       MyCaos.##r2        =(ULONG) v2;            \
  485.       MyCaos.##r3        =(ULONG) v3;            \
  486.       MyCaos.a6            =(ULONG) bn;            \
  487.       MyCaos.M68kCacheMode    =    cm1;            \
  488.       if ((cm1==IF_CACHEFLUSHAREA) || (cm1==IF_CACHEINVALIDAREA))    \
  489.       {                                \
  490.         MyCaos.M68kStart    =    cs1;            \
  491.         MyCaos.M68kLength    =    cl1;            \
  492.       }                                \
  493.       MyCaos.PPCCacheMode    =    cm2;            \
  494.       if ((cm2==IF_CACHEFLUSHAREA) || (cm2==IF_CACHEINVALIDAREA))    \
  495.       {                                \
  496.         MyCaos.PPCStart        =    cs2;            \
  497.         MyCaos.PPCLength    =    cl2;            \
  498.       }                                \
  499.       MyCaos.caos_Un.Offset    =    (-offs);        \
  500.       __asm volatile ("bl PPCCallOS"                \
  501.       : "=r" (_##name##_re)                    \
  502.       : "r" (MyCaosReg)                      \
  503.       : "r0", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12",  "lr", "ctr", "cc", "memory");    \
  504.       _##name##_re;                        \
  505.    }                                \
  506. })
  507.  
  508. /* Only graphics.library/SetCollision() */
  509. #define LP3NRFP(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, bt, bn, fpt, cm1, cs1, cl1, cm2, cs2, cl2 )    \
  510. ({                                \
  511.    typedef fpt;                            \
  512.    struct Caos    MyCaos;                        \
  513.    register struct Caos *MyCaosReg __asm("r3") = &MyCaos;    \
  514.    {                                \
  515.       MyCaos.##r1        =(ULONG) v1;            \
  516.       MyCaos.##r2        =(ULONG) v2;            \
  517.       MyCaos.##r3        =(ULONG) v3;            \
  518.       MyCaos.a6            =(ULONG) bn;            \
  519.       MyCaos.M68kCacheMode    =    cm1;            \
  520.       if ((cm1==IF_CACHEFLUSHAREA) || (cm1==IF_CACHEINVALIDAREA))    \
  521.       {                                \
  522.         MyCaos.M68kStart    =    cs1;            \
  523.         MyCaos.M68kLength    =    cl1;            \
  524.       }                                \
  525.       MyCaos.PPCCacheMode    =    cm2;            \
  526.       if ((cm2==IF_CACHEFLUSHAREA) || (cm2==IF_CACHEINVALIDAREA))    \
  527.       {                                \
  528.         MyCaos.PPCStart        =    cs2;            \
  529.         MyCaos.PPCLength    =    cl2;            \
  530.       }                                \
  531.       MyCaos.caos_Un.Offset    =    (-offs);        \
  532.       __asm volatile ("bl PPCCallOS"                \
  533.       :                                \
  534.       : "r" (MyCaosReg)                      \
  535.       : "r0", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12",  "lr", "ctr", "cc", "memory");    \
  536.    }                                \
  537. })
  538.  
  539. #define LP4(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, bt, bn, cm1, cs1, cl1, cm2, cs2, cl2 )    \
  540. ({                                \
  541.    struct Caos    MyCaos;                        \
  542.    register struct Caos *MyCaosReg __asm("r3") = &MyCaos;    \
  543.    {                                \
  544.       register rt _##name##_re __asm("r3");            \
  545.       MyCaos.##r1        =(ULONG) v1;            \
  546.       MyCaos.##r2        =(ULONG) v2;            \
  547.       MyCaos.##r3        =(ULONG) v3;            \
  548.       MyCaos.##r4        =(ULONG) v4;            \
  549.       MyCaos.a6            =(ULONG) bn;            \
  550.       MyCaos.M68kCacheMode    =    cm1;            \
  551.       if ((cm1==IF_CACHEFLUSHAREA) || (cm1==IF_CACHEINVALIDAREA))    \
  552.       {                                \
  553.         MyCaos.M68kStart    =    cs1;            \
  554.         MyCaos.M68kLength    =    cl1;            \
  555.       }                                \
  556.       MyCaos.PPCCacheMode    =    cm2;            \
  557.       if ((cm2==IF_CACHEFLUSHAREA) || (cm2==IF_CACHEINVALIDAREA))    \
  558.       {                                \
  559.         MyCaos.PPCStart        =    cs2;            \
  560.         MyCaos.PPCLength    =    cl2;            \
  561.       }                                \
  562.       MyCaos.caos_Un.Offset    =    (-offs);        \
  563.       __asm volatile ("bl PPCCallOS"                \
  564.       : "=r" (_##name##_re)                    \
  565.       : "r" (MyCaosReg)                      \
  566.       : "r0", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12",  "lr", "ctr", "cc", "memory");    \
  567.       _##name##_re;                        \
  568.    }                                \
  569. })
  570.  
  571. #define LP4NR(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, bt, bn, cm1, cs1, cl1, cm2, cs2, cl2 )    \
  572. ({                                \
  573.    struct Caos    MyCaos;                        \
  574.    register struct Caos *MyCaosReg __asm("r3") = &MyCaos;    \
  575.    {                                \
  576.       MyCaos.##r1        =(ULONG) v1;            \
  577.       MyCaos.##r2        =(ULONG) v2;            \
  578.       MyCaos.##r3        =(ULONG) v3;            \
  579.       MyCaos.##r4        =(ULONG) v4;            \
  580.       MyCaos.a6            =(ULONG) bn;            \
  581.       MyCaos.M68kCacheMode    =    cm1;            \
  582.       if ((cm1==IF_CACHEFLUSHAREA) || (cm1==IF_CACHEINVALIDAREA))    \
  583.       {                                \
  584.         MyCaos.M68kStart    =    cs1;            \
  585.         MyCaos.M68kLength    =    cl1;            \
  586.       }                                \
  587.       MyCaos.PPCCacheMode    =    cm2;            \
  588.       if ((cm2==IF_CACHEFLUSHAREA) || (cm2==IF_CACHEINVALIDAREA))    \
  589.       {                                \
  590.         MyCaos.PPCStart        =    cs2;            \
  591.         MyCaos.PPCLength    =    cl2;            \
  592.       }                                \
  593.       MyCaos.caos_Un.Offset    =    (-offs);        \
  594.       __asm volatile ("bl PPCCallOS"                \
  595.       :                                \
  596.       : "r" (MyCaosReg)                      \
  597.       : "r0", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12",  "lr", "ctr", "cc", "memory");    \
  598.    }                                \
  599. })
  600.  
  601. /* Only exec.library/RawDoFmt() */
  602. #define LP4FP(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, bt, bn, fpt, cm1, cs1, cl1, cm2, cs2, cl2 )    \
  603. ({                                \
  604.    typedef fpt;                            \
  605.    struct Caos    MyCaos;                        \
  606.    register struct Caos *MyCaosReg __asm("r3") = &MyCaos;    \
  607.    {                                \
  608.       register rt _##name##_re __asm("r3");            \
  609.       MyCaos.##r1        =(ULONG) v1;            \
  610.       MyCaos.##r2        =(ULONG) v2;            \
  611.       MyCaos.##r3        =(ULONG) v3;            \
  612.       MyCaos.##r4        =(ULONG) v4;            \
  613.       MyCaos.a6            =(ULONG) bn;            \
  614.       MyCaos.M68kCacheMode    =    cm1;            \
  615.       if ((cm1==IF_CACHEFLUSHAREA) || (cm1==IF_CACHEINVALIDAREA))    \
  616.       {                                \
  617.         MyCaos.M68kStart    =    cs1;            \
  618.         MyCaos.M68kLength    =    cl1;            \
  619.       }                                \
  620.       MyCaos.PPCCacheMode    =    cm2;            \
  621.       if ((cm2==IF_CACHEFLUSHAREA) || (cm2==IF_CACHEINVALIDAREA))    \
  622.       {                                \
  623.         MyCaos.PPCStart        =    cs2;            \
  624.         MyCaos.PPCLength    =    cl2;            \
  625.       }                                \
  626.       MyCaos.caos_Un.Offset    =    (-offs);        \
  627.       __asm volatile ("bl PPCCallOS"                \
  628.       : "=r" (_##name##_re)                    \
  629.       : "r" (MyCaosReg)                      \
  630.       : "r0", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12",  "lr", "ctr", "cc", "memory");    \
  631.       _##name##_re;                        \
  632.    }                                \
  633. })
  634.  
  635. #define LP5(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, bt, bn, cm1, cs1, cl1, cm2, cs2, cl2 )    \
  636. ({                                \
  637.    struct Caos    MyCaos;                        \
  638.    register struct Caos *MyCaosReg __asm("r3") = &MyCaos;    \
  639.    {                                \
  640.       register rt _##name##_re __asm("r3");            \
  641.       MyCaos.##r1        =(ULONG) v1;            \
  642.       MyCaos.##r2        =(ULONG) v2;            \
  643.       MyCaos.##r3        =(ULONG) v3;            \
  644.       MyCaos.##r4        =(ULONG) v4;            \
  645.       MyCaos.##r5        =(ULONG) v5;            \
  646.       MyCaos.a6            =(ULONG) bn;            \
  647.       MyCaos.M68kCacheMode    =    cm1;            \
  648.       if ((cm1==IF_CACHEFLUSHAREA) || (cm1==IF_CACHEINVALIDAREA))    \
  649.       {                                \
  650.         MyCaos.M68kStart    =    cs1;            \
  651.         MyCaos.M68kLength    =    cl1;            \
  652.       }                                \
  653.       MyCaos.PPCCacheMode    =    cm2;            \
  654.       if ((cm2==IF_CACHEFLUSHAREA) || (cm2==IF_CACHEINVALIDAREA))    \
  655.       {                                \
  656.         MyCaos.PPCStart        =    cs2;            \
  657.         MyCaos.PPCLength    =    cl2;            \
  658.       }                                \
  659.       MyCaos.caos_Un.Offset    =    (-offs);        \
  660.       __asm volatile ("bl PPCCallOS"                \
  661.       : "=r" (_##name##_re)                    \
  662.       : "r" (MyCaosReg)                      \
  663.       : "r0", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12",  "lr", "ctr", "cc", "memory");    \
  664.       _##name##_re;                        \
  665.    }                                \
  666. })
  667.  
  668. #define LP5NR(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, bt, bn, cm1, cs1, cl1, cm2, cs2, cl2 )    \
  669. ({                                \
  670.    struct Caos    MyCaos;                        \
  671.    register struct Caos *MyCaosReg __asm("r3") = &MyCaos;    \
  672.    {                                \
  673.       MyCaos.##r1        =(ULONG) v1;            \
  674.       MyCaos.##r2        =(ULONG) v2;            \
  675.       MyCaos.##r3        =(ULONG) v3;            \
  676.       MyCaos.##r4        =(ULONG) v4;            \
  677.       MyCaos.##r5        =(ULONG) v5;            \
  678.       MyCaos.a6            =(ULONG) bn;            \
  679.       MyCaos.M68kCacheMode    =    cm1;            \
  680.       if ((cm1==IF_CACHEFLUSHAREA) || (cm1==IF_CACHEINVALIDAREA))    \
  681.       {                                \
  682.         MyCaos.M68kStart    =    cs1;            \
  683.         MyCaos.M68kLength    =    cl1;            \
  684.       }                                \
  685.       MyCaos.PPCCacheMode    =    cm2;            \
  686.       if ((cm2==IF_CACHEFLUSHAREA) || (cm2==IF_CACHEINVALIDAREA))    \
  687.       {                                \
  688.         MyCaos.PPCStart        =    cs2;            \
  689.         MyCaos.PPCLength    =    cl2;            \
  690.       }                                \
  691.       MyCaos.caos_Un.Offset    =    (-offs);        \
  692.       __asm volatile ("bl PPCCallOS"                \
  693.       :                                \
  694.       : "r" (MyCaosReg)                      \
  695.       : "r0", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12",  "lr", "ctr", "cc", "memory");    \
  696.    }                                \
  697. })
  698.  
  699. /* Only exec.library/MakeLibrary() */
  700. #define LP5FP(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, bt, bn, fpt, cm1, cs1, cl1, cm2, cs2, cl2 )    \
  701. ({                                \
  702.    typedef fpt;                            \
  703.    struct Caos    MyCaos;                        \
  704.    register struct Caos *MyCaosReg __asm("r3") = &MyCaos;    \
  705.    {                                \
  706.       register rt _##name##_re __asm("r3");            \
  707.       MyCaos.##r1        =(ULONG) v1;            \
  708.       MyCaos.##r2        =(ULONG) v2;            \
  709.       MyCaos.##r3        =(ULONG) v3;            \
  710.       MyCaos.##r4        =(ULONG) v4;            \
  711.       MyCaos.##r5        =(ULONG) v5;            \
  712.       MyCaos.a6            =(ULONG) bn;            \
  713.       MyCaos.M68kCacheMode    =    cm1;            \
  714.       if ((cm1==IF_CACHEFLUSHAREA) || (cm1==IF_CACHEINVALIDAREA))    \
  715.       {                                \
  716.         MyCaos.M68kStart    =    cs1;            \
  717.         MyCaos.M68kLength    =    cl1;            \
  718.       }                                \
  719.       MyCaos.PPCCacheMode    =    cm2;            \
  720.       if ((cm2==IF_CACHEFLUSHAREA) || (cm2==IF_CACHEINVALIDAREA))    \
  721.       {                                \
  722.         MyCaos.PPCStart        =    cs2;            \
  723.         MyCaos.PPCLength    =    cl2;            \
  724.       }                                \
  725.       MyCaos.caos_Un.Offset    =    (-offs);        \
  726.       __asm volatile ("bl PPCCallOS"                \
  727.       : "=r" (_##name##_re)                    \
  728.       : "r" (MyCaosReg)                      \
  729.       : "r0", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12",  "lr", "ctr", "cc", "memory");    \
  730.       _##name##_re;                        \
  731.    }                                \
  732. })
  733.  
  734. #define LP6(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, bt, bn, cm1, cs1, cl1, cm2, cs2, cl2 )    \
  735. ({                                \
  736.    struct Caos    MyCaos;                        \
  737.    register struct Caos *MyCaosReg __asm("r3") = &MyCaos;    \
  738.    {                                \
  739.       register rt _##name##_re __asm("r3");            \
  740.       MyCaos.##r1        =(ULONG) v1;            \
  741.       MyCaos.##r2        =(ULONG) v2;            \
  742.       MyCaos.##r3        =(ULONG) v3;            \
  743.       MyCaos.##r4        =(ULONG) v4;            \
  744.       MyCaos.##r5        =(ULONG) v5;            \
  745.       MyCaos.##r6        =(ULONG) v6;            \
  746.       MyCaos.a6            =(ULONG) bn;            \
  747.       MyCaos.M68kCacheMode    =    cm1;            \
  748.       if ((cm1==IF_CACHEFLUSHAREA) || (cm1==IF_CACHEINVALIDAREA))    \
  749.       {                                \
  750.         MyCaos.M68kStart    =    cs1;            \
  751.         MyCaos.M68kLength    =    cl1;            \
  752.       }                                \
  753.       MyCaos.PPCCacheMode    =    cm2;            \
  754.       if ((cm2==IF_CACHEFLUSHAREA) || (cm2==IF_CACHEINVALIDAREA))    \
  755.       {                                \
  756.         MyCaos.PPCStart        =    cs2;            \
  757.         MyCaos.PPCLength    =    cl2;            \
  758.       }                                \
  759.       MyCaos.caos_Un.Offset    =    (-offs);        \
  760.       __asm volatile ("bl PPCCallOS"                \
  761.       : "=r" (_##name##_re)                    \
  762.       : "r" (MyCaosReg)                      \
  763.       : "r0", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12",  "lr", "ctr", "cc", "memory");    \
  764.       _##name##_re;                        \
  765.    }                                \
  766. })
  767.  
  768. #define LP6NR(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, bt, bn, cm1, cs1, cl1, cm2, cs2, cl2 )    \
  769. ({                                \
  770.    struct Caos    MyCaos;                        \
  771.    register struct Caos *MyCaosReg __asm("r3") = &MyCaos;    \
  772.    {                                \
  773.       MyCaos.##r1        =(ULONG) v1;            \
  774.       MyCaos.##r2        =(ULONG) v2;            \
  775.       MyCaos.##r3        =(ULONG) v3;            \
  776.       MyCaos.##r4        =(ULONG) v4;            \
  777.       MyCaos.##r5        =(ULONG) v5;            \
  778.       MyCaos.##r6        =(ULONG) v6;            \
  779.       MyCaos.a6            =(ULONG) bn;            \
  780.       MyCaos.M68kCacheMode    =    cm1;            \
  781.       if ((cm1==IF_CACHEFLUSHAREA) || (cm1==IF_CACHEINVALIDAREA))    \
  782.       {                                \
  783.         MyCaos.M68kStart    =    cs1;            \
  784.         MyCaos.M68kLength    =    cl1;            \
  785.       }                                \
  786.       MyCaos.PPCCacheMode    =    cm2;            \
  787.       if ((cm2==IF_CACHEFLUSHAREA) || (cm2==IF_CACHEINVALIDAREA))    \
  788.       {                                \
  789.         MyCaos.PPCStart        =    cs2;            \
  790.         MyCaos.PPCLength    =    cl2;            \
  791.       }                                \
  792.       MyCaos.caos_Un.Offset    =    (-offs);        \
  793.       __asm volatile ("bl PPCCallOS"                \
  794.       :                                \
  795.       : "r" (MyCaosReg)                      \
  796.       : "r0", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12",  "lr", "ctr", "cc", "memory");    \
  797.    }                                \
  798. })
  799.  
  800. #define LP7(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, bt, bn, cm1, cs1, cl1, cm2, cs2, cl2 )    \
  801. ({                                \
  802.    struct Caos    MyCaos;                        \
  803.    register struct Caos *MyCaosReg __asm("r3") = &MyCaos;    \
  804.    {                                \
  805.       register rt _##name##_re __asm("r3");            \
  806.       MyCaos.##r1        =(ULONG) v1;            \
  807.       MyCaos.##r2        =(ULONG) v2;            \
  808.       MyCaos.##r3        =(ULONG) v3;            \
  809.       MyCaos.##r4        =(ULONG) v4;            \
  810.       MyCaos.##r5        =(ULONG) v5;            \
  811.       MyCaos.##r6        =(ULONG) v6;            \
  812.       MyCaos.##r7        =(ULONG) v7;            \
  813.       MyCaos.a6            =(ULONG) bn;            \
  814.       MyCaos.M68kCacheMode    =    cm1;            \
  815.       if ((cm1==IF_CACHEFLUSHAREA) || (cm1==IF_CACHEINVALIDAREA))    \
  816.       {                                \
  817.         MyCaos.M68kStart    =    cs1;            \
  818.         MyCaos.M68kLength    =    cl1;            \
  819.       }                                \
  820.       MyCaos.PPCCacheMode    =    cm2;            \
  821.       if ((cm2==IF_CACHEFLUSHAREA) || (cm2==IF_CACHEINVALIDAREA))    \
  822.       {                                \
  823.         MyCaos.PPCStart        =    cs2;            \
  824.         MyCaos.PPCLength    =    cl2;            \
  825.       }                                \
  826.       MyCaos.caos_Un.Offset    =    (-offs);        \
  827.       __asm volatile ("bl PPCCallOS"                \
  828.       : "=r" (_##name##_re)                    \
  829.       : "r" (MyCaosReg)                      \
  830.       : "r0", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12",  "lr", "ctr", "cc", "memory");    \
  831.       _##name##_re;                        \
  832.    }                                \
  833. })
  834.  
  835. #define LP7NR(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, bt, bn, cm1, cs1, cl1, cm2, cs2, cl2 )    \
  836. ({                                \
  837.    struct Caos    MyCaos;                        \
  838.    register struct Caos *MyCaosReg __asm("r3") = &MyCaos;    \
  839.    {                                \
  840.       MyCaos.##r1        =(ULONG) v1;            \
  841.       MyCaos.##r2        =(ULONG) v2;            \
  842.       MyCaos.##r3        =(ULONG) v3;            \
  843.       MyCaos.##r4        =(ULONG) v4;            \
  844.       MyCaos.##r5        =(ULONG) v5;            \
  845.       MyCaos.##r6        =(ULONG) v6;            \
  846.       MyCaos.##r7        =(ULONG) v7;            \
  847.       MyCaos.a6            =(ULONG) bn;            \
  848.       MyCaos.M68kCacheMode    =    cm1;            \
  849.       if ((cm1==IF_CACHEFLUSHAREA) || (cm1==IF_CACHEINVALIDAREA))    \
  850.       {                                \
  851.         MyCaos.M68kStart    =    cs1;            \
  852.         MyCaos.M68kLength    =    cl1;            \
  853.       }                                \
  854.       MyCaos.PPCCacheMode    =    cm2;            \
  855.       if ((cm2==IF_CACHEFLUSHAREA) || (cm2==IF_CACHEINVALIDAREA))    \
  856.       {                                \
  857.         MyCaos.PPCStart        =    cs2;            \
  858.         MyCaos.PPCLength    =    cl2;            \
  859.       }                                \
  860.       MyCaos.caos_Un.Offset    =    (-offs);        \
  861.       __asm volatile ("bl PPCCallOS"                \
  862.       :                                \
  863.       : "r" (MyCaosReg)                      \
  864.       : "r0", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12",  "lr", "ctr", "cc", "memory");    \
  865.    }                                \
  866. })
  867.  
  868. /* Only workbench.library/AddAppIconA() */
  869. #define LP7A4(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, bt, bn, cm1, cs1, cl1, cm2, cs2, cl2 )    \
  870. ({                                \
  871.    struct Caos    MyCaos;                        \
  872.    register struct Caos *MyCaosReg __asm("r3") = &MyCaos;    \
  873.    {                                \
  874.       register rt _##name##_re __asm("r3");            \
  875.       MyCaos.##r1        =(ULONG) v1;            \
  876.       MyCaos.##r2        =(ULONG) v2;            \
  877.       MyCaos.##r3        =(ULONG) v3;            \
  878.       MyCaos.##r4        =(ULONG) v4;            \
  879.       MyCaos.##r5        =(ULONG) v5;            \
  880.       MyCaos.##r6        =(ULONG) v6;            \
  881.       MyCaos.##r7        =(ULONG) v7;            \
  882.       MyCaos.a6            =(ULONG) bn;            \
  883.       MyCaos.M68kCacheMode    =    cm1;            \
  884.       if ((cm1==IF_CACHEFLUSHAREA) || (cm1==IF_CACHEINVALIDAREA))    \
  885.       {                                \
  886.         MyCaos.M68kStart    =    cs1;            \
  887.         MyCaos.M68kLength    =    cl1;            \
  888.       }                                \
  889.       MyCaos.PPCCacheMode    =    cm2;            \
  890.       if ((cm2==IF_CACHEFLUSHAREA) || (cm2==IF_CACHEINVALIDAREA))    \
  891.       {                                \
  892.         MyCaos.PPCStart        =    cs2;            \
  893.         MyCaos.PPCLength    =    cl2;            \
  894.       }                                \
  895.       MyCaos.caos_Un.Offset    =    (-offs);        \
  896.       __asm volatile ("bl PPCCallOS"                \
  897.       : "=r" (_##name##_re)                    \
  898.       : "r" (MyCaosReg)                      \
  899.       : "r0", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12",  "lr", "ctr", "cc", "memory");    \
  900.       _##name##_re;                        \
  901.    }                                \
  902. })
  903.  
  904. /* Would you believe that there really are beasts that need more than 7
  905.    arguments? :-) */
  906.  
  907. /* For example intuition.library/AutoRequest() */
  908. #define LP8(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, t8, v8, r8, bt, bn, cm1, cs1, cl1, cm2, cs2, cl2 )    \
  909. ({                                \
  910.    struct Caos    MyCaos;                        \
  911.    register struct Caos *MyCaosReg __asm("r3") = &MyCaos;    \
  912.    {                                \
  913.       register rt _##name##_re __asm("r3");            \
  914.       MyCaos.##r1        =(ULONG) v1;            \
  915.       MyCaos.##r2        =(ULONG) v2;            \
  916.       MyCaos.##r3        =(ULONG) v3;            \
  917.       MyCaos.##r4        =(ULONG) v4;            \
  918.       MyCaos.##r5        =(ULONG) v5;            \
  919.       MyCaos.##r6        =(ULONG) v6;            \
  920.       MyCaos.##r7        =(ULONG) v7;            \
  921.       MyCaos.##r8        =(ULONG) v8;            \
  922.       MyCaos.a6            =(ULONG) bn;            \
  923.       MyCaos.M68kCacheMode    =    cm1;            \
  924.       if ((cm1==IF_CACHEFLUSHAREA) || (cm1==IF_CACHEINVALIDAREA))    \
  925.       {                                \
  926.         MyCaos.M68kStart    =    cs1;            \
  927.         MyCaos.M68kLength    =    cl1;            \
  928.       }                                \
  929.       MyCaos.PPCCacheMode    =    cm2;            \
  930.       if ((cm2==IF_CACHEFLUSHAREA) || (cm2==IF_CACHEINVALIDAREA))    \
  931.       {                                \
  932.         MyCaos.PPCStart        =    cs2;            \
  933.         MyCaos.PPCLength    =    cl2;            \
  934.       }                                \
  935.       MyCaos.caos_Un.Offset    =    (-offs);        \
  936.       __asm volatile ("bl PPCCallOS"                \
  937.       : "=r" (_##name##_re)                    \
  938.       : "r" (MyCaosReg)                      \
  939.       : "r0", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12",  "lr", "ctr", "cc", "memory");    \
  940.       _##name##_re;                        \
  941.    }                                \
  942. })
  943.  
  944. /* For example intuition.library/ModifyProp() */
  945. #define LP8NR(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, t8, v8, r8, bt, bn, cm1, cs1, cl1, cm2, cs2, cl2 )    \
  946. ({                                \
  947.    struct Caos    MyCaos;                        \
  948.    register struct Caos *MyCaosReg __asm("r3") = &MyCaos;    \
  949.    {                                \
  950.       MyCaos.##r1        =(ULONG) v1;            \
  951.       MyCaos.##r2        =(ULONG) v2;            \
  952.       MyCaos.##r3        =(ULONG) v3;            \
  953.       MyCaos.##r4        =(ULONG) v4;            \
  954.       MyCaos.##r5        =(ULONG) v5;            \
  955.       MyCaos.##r6        =(ULONG) v6;            \
  956.       MyCaos.##r7        =(ULONG) v7;            \
  957.       MyCaos.##r8        =(ULONG) v8;            \
  958.       MyCaos.a6            =(ULONG) bn;            \
  959.       MyCaos.M68kCacheMode    =    cm1;            \
  960.       if ((cm1==IF_CACHEFLUSHAREA) || (cm1==IF_CACHEINVALIDAREA))    \
  961.       {                                \
  962.         MyCaos.M68kStart    =    cs1;            \
  963.         MyCaos.M68kLength    =    cl1;            \
  964.       }                                \
  965.       MyCaos.PPCCacheMode    =    cm2;            \
  966.       if ((cm2==IF_CACHEFLUSHAREA) || (cm2==IF_CACHEINVALIDAREA))    \
  967.       {                                \
  968.         MyCaos.PPCStart        =    cs2;            \
  969.         MyCaos.PPCLength    =    cl2;            \
  970.       }                                \
  971.       MyCaos.caos_Un.Offset    =    (-offs);        \
  972.       __asm volatile ("bl PPCCallOS"                \
  973.       :                                \
  974.       : "r" (MyCaosReg)                      \
  975.       : "r0", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12",  "lr", "ctr", "cc", "memory");    \
  976.    }                                \
  977. })
  978.  
  979. /* For example layers.library/CreateUpfrontHookLayer() */
  980. #define LP9(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, t8, v8, r8, t9, v9, r9, bt, bn, cm1, cs1, cl1, cm2, cs2, cl2 )    \
  981. ({                                \
  982.    struct Caos    MyCaos;                        \
  983.    register struct Caos *MyCaosReg __asm("r3") = &MyCaos;    \
  984.    {                                \
  985.       register rt _##name##_re __asm("r3");            \
  986.       MyCaos.##r1        =(ULONG) v1;            \
  987.       MyCaos.##r2        =(ULONG) v2;            \
  988.       MyCaos.##r3        =(ULONG) v3;            \
  989.       MyCaos.##r4        =(ULONG) v4;            \
  990.       MyCaos.##r5        =(ULONG) v5;            \
  991.       MyCaos.##r6        =(ULONG) v6;            \
  992.       MyCaos.##r7        =(ULONG) v7;            \
  993.       MyCaos.##r8        =(ULONG) v8;            \
  994.       MyCaos.##r9        =(ULONG) v9;            \
  995.       MyCaos.a6            =(ULONG) bn;            \
  996.       MyCaos.M68kCacheMode    =    cm1;            \
  997.       if ((cm1==IF_CACHEFLUSHAREA) || (cm1==IF_CACHEINVALIDAREA))    \
  998.       {                                \
  999.         MyCaos.M68kStart    =    cs1;            \
  1000.         MyCaos.M68kLength    =    cl1;            \
  1001.       }                                \
  1002.       MyCaos.PPCCacheMode    =    cm2;            \
  1003.       if ((cm2==IF_CACHEFLUSHAREA) || (cm2==IF_CACHEINVALIDAREA))    \
  1004.       {                                \
  1005.         MyCaos.PPCStart        =    cs2;            \
  1006.         MyCaos.PPCLength    =    cl2;            \
  1007.       }                                \
  1008.       MyCaos.caos_Un.Offset    =    (-offs);        \
  1009.       __asm volatile ("bl PPCCallOS"                \
  1010.       : "=r" (_##name##_re)                    \
  1011.       : "r" (MyCaosReg)                      \
  1012.       : "r0", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12",  "lr", "ctr", "cc", "memory");    \
  1013.       _##name##_re;                        \
  1014.    }                                \
  1015. })
  1016.  
  1017. /* For example intuition.library/NewModifyProp() */
  1018. #define LP9NR(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, t8, v8, r8, t9, v9, r9, bt, bn, cm1, cs1, cl1, cm2, cs2, cl2 )    \
  1019. ({                                \
  1020.    struct Caos    MyCaos;                        \
  1021.    register struct Caos *MyCaosReg __asm("r3") = &MyCaos;    \
  1022.    {                                \
  1023.       MyCaos.##r1        =(ULONG) v1;            \
  1024.       MyCaos.##r2        =(ULONG) v2;            \
  1025.       MyCaos.##r3        =(ULONG) v3;            \
  1026.       MyCaos.##r4        =(ULONG) v4;            \
  1027.       MyCaos.##r5        =(ULONG) v5;            \
  1028.       MyCaos.##r6        =(ULONG) v6;            \
  1029.       MyCaos.##r7        =(ULONG) v7;            \
  1030.       MyCaos.##r8        =(ULONG) v8;            \
  1031.       MyCaos.##r9        =(ULONG) v9;            \
  1032.       MyCaos.a6            =(ULONG) bn;            \
  1033.       MyCaos.M68kCacheMode    =    cm1;            \
  1034.       if ((cm1==IF_CACHEFLUSHAREA) || (cm1==IF_CACHEINVALIDAREA))    \
  1035.       {                                \
  1036.         MyCaos.M68kStart    =    cs1;            \
  1037.         MyCaos.M68kLength    =    cl1;            \
  1038.       }                                \
  1039.       MyCaos.PPCCacheMode    =    cm2;            \
  1040.       if ((cm2==IF_CACHEFLUSHAREA) || (cm2==IF_CACHEINVALIDAREA))    \
  1041.       {                                \
  1042.         MyCaos.PPCStart        =    cs2;            \
  1043.         MyCaos.PPCLength    =    cl2;            \
  1044.       }                                \
  1045.       MyCaos.caos_Un.Offset    =    (-offs);        \
  1046.       __asm volatile ("bl PPCCallOS"                \
  1047.       :                                \
  1048.       : "r" (MyCaosReg)                      \
  1049.       : "r0", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12",  "lr", "ctr", "cc", "memory");    \
  1050.    }                                \
  1051. })
  1052.  
  1053. /* LP10 not needed... */
  1054.  
  1055. /* Only graphics.library/BltMaskBitMapRastPort() */
  1056. #define LP10NR(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, t8, v8, r8, t9, v9, r9, t10, v10, r10, bt, bn, cm1, cs1, cl1, cm2, cs2, cl2 )    \
  1057. ({                                \
  1058.    struct Caos    MyCaos;                        \
  1059.    register struct Caos *MyCaosReg __asm("r3") = &MyCaos;    \
  1060.    {                                \
  1061.       MyCaos.##r1        =(ULONG) v1;            \
  1062.       MyCaos.##r2        =(ULONG) v2;            \
  1063.       MyCaos.##r3        =(ULONG) v3;            \
  1064.       MyCaos.##r4        =(ULONG) v4;            \
  1065.       MyCaos.##r5        =(ULONG) v5;            \
  1066.       MyCaos.##r6        =(ULONG) v6;            \
  1067.       MyCaos.##r7        =(ULONG) v7;            \
  1068.       MyCaos.##r8        =(ULONG) v8;            \
  1069.       MyCaos.##r9        =(ULONG) v9;            \
  1070.       MyCaos.##r10        =(ULONG) v10;            \
  1071.       MyCaos.a6            =(ULONG) bn;            \
  1072.       MyCaos.M68kCacheMode    =    cm1;            \
  1073.       if ((cm1==IF_CACHEFLUSHAREA) || (cm1==IF_CACHEINVALIDAREA))    \
  1074.       {                                \
  1075.         MyCaos.M68kStart    =    cs1;            \
  1076.         MyCaos.M68kLength    =    cl1;            \
  1077.       }                                \
  1078.       MyCaos.PPCCacheMode    =    cm2;            \
  1079.       if ((cm2==IF_CACHEFLUSHAREA) || (cm2==IF_CACHEINVALIDAREA))    \
  1080.       {                                \
  1081.         MyCaos.PPCStart        =    cs2;            \
  1082.         MyCaos.PPCLength    =    cl2;            \
  1083.       }                                \
  1084.       MyCaos.caos_Un.Offset    =    (-offs);        \
  1085.       __asm volatile ("bl PPCCallOS"                \
  1086.       :                                \
  1087.       : "r" (MyCaosReg)                      \
  1088.       : "r0", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12",  "lr", "ctr", "cc", "memory");    \
  1089.    }                                \
  1090. })
  1091.  
  1092. /* Only graphics.library/BltBitMap() */
  1093. #define LP11(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, t8, v8, r8, t9, v9, r9, t10, v10, r10, t11, v11, r11, bt, bn, cm1, cs1, cl1, cm2, cs2, cl2 )    \
  1094. ({                                \
  1095.    struct Caos    MyCaos;                        \
  1096.    register struct Caos *MyCaosReg __asm("r3") = &MyCaos;    \
  1097.    {                                \
  1098.       register rt _##name##_re __asm("r3");            \
  1099.       MyCaos.##r1        =(ULONG) v1;            \
  1100.       MyCaos.##r2        =(ULONG) v2;            \
  1101.       MyCaos.##r3        =(ULONG) v3;            \
  1102.       MyCaos.##r4        =(ULONG) v4;            \
  1103.       MyCaos.##r5        =(ULONG) v5;            \
  1104.       MyCaos.##r6        =(ULONG) v6;            \
  1105.       MyCaos.##r7        =(ULONG) v7;            \
  1106.       MyCaos.##r8        =(ULONG) v8;            \
  1107.       MyCaos.##r9        =(ULONG) v9;            \
  1108.       MyCaos.##r10        =(ULONG) v10;            \
  1109.       MyCaos.##r11        =(ULONG) v11;            \
  1110.       MyCaos.a6            =(ULONG) bn;            \
  1111.       MyCaos.M68kCacheMode    =    cm1;            \
  1112.       if ((cm1==IF_CACHEFLUSHAREA) || (cm1==IF_CACHEINVALIDAREA))    \
  1113.       {                                \
  1114.         MyCaos.M68kStart    =    cs1;            \
  1115.         MyCaos.M68kLength    =    cl1;            \
  1116.       }                                \
  1117.       MyCaos.PPCCacheMode    =    cm2;            \
  1118.       if ((cm2==IF_CACHEFLUSHAREA) || (cm2==IF_CACHEINVALIDAREA))    \
  1119.       {                                \
  1120.         MyCaos.PPCStart        =    cs2;            \
  1121.         MyCaos.PPCLength    =    cl2;            \
  1122.       }                                \
  1123.       MyCaos.caos_Un.Offset    =    (-offs);        \
  1124.       __asm volatile ("bl PPCCallOS"                \
  1125.       : "=r" (_##name##_re)                    \
  1126.       : "r" (MyCaosReg)                      \
  1127.       : "r0", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12",  "lr", "ctr", "cc", "memory");    \
  1128.       _##name##_re;                        \
  1129.    }                                \
  1130. })
  1131.  
  1132. #endif /* __INLINE_MACROS_H */
  1133.